The present invention relates to transcoding of digital video signals, and in particular, to providing an accurate time reference for the input and output signals of a transcoder.
Commonly, it is necessary to adjust a bit rate of digital video programs that are provided, e.g., to subscriber terminals in a cable television network or the like. For example, a first group of signals may be received at a headend via a satellite transmission. The headend operator may desire to forward selected programs to the subscribers while adding programs (e.g., commercials or other content) from a local source, such as storage media or a local live feed. Additionally, it is often necessary to provide the programs within an overall available channel bandwidth.
Accordingly, the statistical remultiplexer (stat remux), or transcoder, which handles pre-compressed video bit streams by re-compressing them at a specified bit rate, has been developed. Similarly, the stat mux handles uncompressed video data by compressing it at a desired bit rate.
In such systems, a number of channels of data are processed by a number of processors arranged in parallel. Each processor typically can accommodate multiple channels of data. Although, in some cases, such as for HDTV, which require many computations, portions of data from a single channel are allocated among multiple processors.
Single-channel transcoders are also used in various applications.
In a digital video compression system, such as the MPEG-2 system, the digital video source is clocked at 27 MHz (D1 video standard). The decoder must generate the same 27 MHz clock such that the encoder and decoder clocks are locked. This clock is referred to as the System Time Clock (STC). Both the encoder and decoder have a counter that is incremented on each tick of the STC. When the encoder and decoder STCs are synchronized, both counters are the same value.
To synchronize the decoder, the encoder sends a PCR (Program Clock Reference) to the decoder. The PCR is the value of the STC counter at the instant the packet with the PCR leaves the encoder. When the packet with the PCR is received by the decoder, the decoder compares this value with its STC counter value. If the two are the same, no adjustment is needed. If the two values are different, the decoder must either reset, speed up, or slow down its STC.
In various transcoding applications, the processing acts like multiple pairs of decoders encoders are used since each input video channel is transcoded (e.g., decoded and re-encoded). Thus, the input STC must be recovered for each channel, and a new PCR must then be output for the re-encoded output. One possible solution is to have one local STC for each video service that is received. However, this is expensive since it requires a phase-locked loop (PLL) for every video service.
Accordingly, it would be desirable to provide a cost-effective and efficient system for recovering an input STC from each channel in a transcoder, and outputting a new PCR for the re-encoded output.
The system should use only one master STC, and correct for the differences between the master STC and the STCs of the different services or channels.
The system should be implementable in software.
The system should avoid the need for multiple counters.
The system should correct for a frequency difference between the master STC and input STC.
The system should also account for changes in Decoding Time Stamps (DTSs) and Presentation Time Stamps (PTSs).
A lookahead delay at a transcoder, and buffer delays of an encoder of the transcoder and of an end user decoder, should also be accounted for.
The present invention provides a system having the above and other advantages.
The present invention relates to providing an accurate time reference for the input and output digital video signals of a transcoder.
Instead of using one local STC clock for each video service that is received, the invention uses only one master STC. The differences between the master STC and the service""s input STC are then corrected, e.g., using software.
Advantageously, an offset between the master STC and input PCRs is computed to avoid multiple counters. A frequency difference between the master STC and input STC is then computed. This frequency difference is corrected when computing the output PCR.
In addition, the invention also corrects the PTSs and DTSs, which inform a decoder when to present (display) and decode a picture, respectively, whether the decoder is part of a transcoder, or a stand alone end user""s decoder, such as in a set-top box. In particular, the DTS references the PCR. For example, when the PCR equals the DTS for a picture, that picture is decoded. The computed STC is referenced at the input to the transcoder. A video frame is delayed by a fixed amount due the transcoding delay. This delay is the time of the original PTS/DTS of the input stream until the time of the transcoded PTS/DTS. Therefore, the original PTS and DTS must be adjusted by adding in this delay. However, instead of modifying both the PCR and the time stamps (PTS and DTS), we subtract this delay from the PCR to create the same effect.
A method in accordance with the invention for providing adjusted timing data for a plurality of respective channels that are input to a transcoder, includes the step of, for each channel, recovering timing data (PcrIn) from at least one packet thereof that is input to the transcoder at a respective input time, and determining an associated offset (PcrOffset) between the recovered timing data (PcrIn) and timing data (PcrInHwTag) of a master system time clock of the transcoder at the respective input time. Additionally, for each channel, adjusted timing data (PcrOut) is provided in at least one packet thereof that is output from the transcoder at a respective output time according to the associated offset (PcrOffset), and timing data (PcrOutHwTag) of the master system time clock at the respective output time.
Moreover, the adjusted timing data (PcrOut) is further provided in the at least one packet that is output from the transcoder according to a sum of the associated offset and an associated hardware error (PcrHwErr), less a delay (PcrSysDly) associated with the transcoder.
The associated hardware error (PcrHwErr) is associated with: (a) the master system time clock and (b) a system time clock of an encoder that encoded the particular channel, and the delay (PcrSysDly) associated with the transcoder includes a lookahead delay (lookahead_dly) and a buffer delay (buffer_dly).
A corresponding apparatus is also presented.